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R8C/3JA Group
RENESAS MCU
REJ03B0263-0110 Rev.1.10 Sep 30, 2009
1.
1.1
Overview
Features
The R8C/3JA Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. The R8C/3JA Group has data flash (1 KB x 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 1 of 54
R8C/3JA Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/3JA Group. Table 1.1
Item CPU
Specifications for R8C/3JA Group (1)
Function Central processing unit Specification R8C CPU core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.3 Product List for R8C/3JA Group. * Power-on reset * Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) * Input-only: 1 pin * CMOS I/O ports: 31, selectable pull-up resistor * High current drive ports: 31 * 3 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit (32 kHz), Low-speed on-chip oscillator * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, low-speed clock, low-speed onchip oscillator), wait mode, stop mode Real-time clock (timer RE) * Number of interrupt vectors: 69 * External Interrupt: 8 (INT x 4, Key input x 4) * Priority levels: 7 levels * 14 bits x 1 (with prescaler) * Reset start selectable * Low-speed on-chip oscillator for watchdog timer selectable * 1 channel * Activation sources: 32 * Transfer modes: 2 (normal mode, repeat mode) 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits x 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) 8 bits x 1 Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode
Memory
ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
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R8C/3JA Group
1. Overview
Table 1.2
Item Serial Interface
Specifications for R8C/3JA Group (2)
Function UART0, UART1 UART2 Specification Clock synchronous serial I/O/UART x 2 channel Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor communication function 1 (shared with I2C-bus) 1 (shared with SSU) Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 10 channels, includes sample and hold function, with sweep mode 8-bit resolution x 2 circuits * 2 circuits (shared with voltage monitor 1 and voltage monitor 2) * External reference voltage input available 2 circuits * Programming and erasure voltage: VCC = 2.7 to 5.5 V * Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function * Background operation (BGO) function f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V) Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 3.5 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) Typ. 2.0 A (VCC = 3.0 V, stop mode) -20 to 85C (N version) 36-pin HWQFN Package code: PWQN0036KA-B (previous code: 36PJW-B)
Synchronous Serial Communication Unit (SSU) I2C bus LIN Module A/D Converter D/A Converter Comparator A Comparator B Flash Memory
Operating Frequency/Supply Voltage Current consumption
Operating Ambient Temperature Package
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R8C/3JA Group
1. Overview
1.2
Product List
Table 1.3 lists Product List for R8C/3JA Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/3JA Group. Table 1.3 Product List for R8C/3JA Group ROM Capacity Program ROM Data flash 8 Kbytes 1 Kbyte x 4 16 Kbytes 24 Kbytes 32 Kbytes 1 Kbyte x 4 1 Kbyte x 4 1 Kbyte x 4 RAM Capacity 1 Kbyte 1.5 Kbytes 2 Kbytes 2.5 Kbytes Current of Sep. 2009 Package Type PWQN0036KA-B PWQN0036KA-B PWQN0036KA-B PWQN0036KA-B Remarks N version
Part No. R5F213J2ANNP R5F213J4ANNP R5F213J5ANNP R5F213J6ANNP
Part No.
R 5 F 21 3J 6 A N NP
Package type: NP: PWQN0036KA-B (0.5 mm pin-pitch, 6 mm square body) Classification N: Operating ambient temperature -20C to 85C ROM capacity 2: 8 KB 4: 16 KB 5: 24 KB 6: 32 KB R8C/3JA Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/3JA Group
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R8C/3JA Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a Block Diagram.
6
8
6
5
5
1
1
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P6
Peripheral functions
Timers Timer RA (8 bits x 1) Timer RB (8 bits x 1) Timer RC (16 bits x 1) Timer RD (16 bits x 2) Timer RE (8 bits x 1) UART or clock synchronous serial I/O (8 bits x 3) I2C bus or SSU (8 bits x 1) System clock generation circuit XIN-XOUT Low-speed on-chip oscillator XCIN-XCOUT
LIN module Watchdog timer (14 bits) A/D converter (10 bits x 10 channels) D/A converter (8 bits x 2) Low-speed on-chip oscillator for watchdog timer Comparator B Voltage detection circuit
Comparator A
DTC
R8C CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM (1)
RAM (2)
Multiplier
Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
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R8C/3JA Group
1. Overview
1.4
Pin Assignment
Figure 1.3 shows the Pin Assignment (Top View). Tables 1.4 and 1.5 outlines the Pin Name Information by Pin Number.
P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)
27 26 25 24 23 22 21 20 19
P1_0/AN8/LVCMP1/KI0(/TRCIOD) P0_7/AN0/DA1(/TRCIOC) P0_6/AN1/DA0(/TRCIOD) P0_4/AN3/TREO(/TRCIOB) P0_3/AN4(/CLK1/TRCIOB) P0_2/AN5(/RXD1/TRCIOA/TRCTRG) P0_1/AN6(/TXD1/TRCIOA/TRCTRG) P4_2/VREF MODE
28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9
P6_6/INT2(/TXD2/SDA2/TRCIOC)
18 17 16
P1_2/AN10/LVREF/Kl2(/TRCIOB)
P4_5/ADTRG/INT0(/RXD2/SCL2)
P1_6/LVCOUT2/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
P1_5(/INT1/RXD0/TRAIO)
P1_4(/TXD0/TRCCLK)
P3_1(/TRBO) P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK) P2_1(/TRCIOC/TRDIOC0) P2_2(/TRCIOD/TRDIOB0) P2_3(/TRDIOD0) P2_4(/TRDIOA1) P2_5(/TRDIOB1) P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK) P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC/TRDIOC1/SDA)
R8C/3JA Group
PWQN0036KA-B(36PJW-B) (top view)
15 14 13 12 11 10
Notes: 1. Can be assigned to the pin in parentheses by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 6 of 54
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2) P3_5/SCL/SSCK(/CLK2/TRCIOD/TRDIOD1)
VSS/AVSS P4_6/XIN
P4_3(/XCIN)
P4_4(/XCOUT)
P4_7/XOUT
VCC/AVCC
RESET
R8C/3JA Group
1. Overview
Table 1.4
Pin Name Information by Pin Number (1)
I/O Pin Functions for Peripheral Modules A/D Converter, D/A Converter, I2C Comparator A, bus Comparator B, Voltage Detection Circuit
Pin Number
Control Pin
Port
Interrupt
Timer
Serial Interface
SSU
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
(XCIN) (XCOUT) RESET XOUT VSS/AVSS XIN VCC/AVCC
P4_3 P4_4 P4_7 P4_6 P3_7 P3_5 P3_4 P3_3 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 (INT1) INT3 TRAO (TRCIOD/ TRDIOD1) (TRCIOC/ TRDIOC1) (TRCCLK) (RXD2/SCL2/ SSO SDA TXD2/SDA2) (CLK2) SSCK SCL (RXD2/SCL2/ TXD2/SDA2) (CTS2/RTS2) SSI SCS SDA IVREF3 IVCMP3
18 19 20 21 22 23 24 25 26 27 28 29 30
P3_1 P6_6 P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6
INT2 INT0 INT1 (INT1) KI3 KI2 KI1 KI0
(TRDIOB1) (TRDIOA1) (TRDIOD0) (TRCIOD/ TRDIOB0) (TRCIOC/ TRDIOC0) (TRCIOB/ TRDIOA0/ TRDCLK) (TRBO) (TRCIOC) (TXD2/SDA2) (RXD2/SCL2) (TRAIO) (TRAIO) (TRCCLK) TRBO/ (TRCIOC) (TRCIOB) (TRCIOA/ TRCTRG) (TRCIOD) (TRCIOC) (TRCIOD) (CLK0) (RXD0) (TXD0) AN11/LVCOUT1 AN10/LVREF AN9/LVCMP2 AN8/LVCMP1 AN0/DA1 AN1/DA0 ADTRG IVCMP1 LVCOUT2/IVREF1
Note: 1. Can be assigned to the pin in parentheses by a program.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 7 of 54
R8C/3JA Group
1. Overview
Table 1.5
Pin Name Information by Pin Number (2)
I/O Pin Functions for Peripheral Modules A/D Converter, D/A Converter, I2C Comparator A, bus Comparator B, Voltage Detection Circuit AN3 (CLK1) (RXD1) (TXD1) AN4 AN5 AN6 VREF
Pin Number
Control Pin
Port
Interrupt
Timer
Serial Interface
SSU
31 32 33 34 35 36
P0_4 P0_3 P0_2 P0_1 P4_2 MODE
TREO/ (TRCIOB) (TRCIOB) (TRCIOA/ TRCTRG) (TRCIOA/ TRCTRG)
Note: 1. Can be assigned to the pin in parentheses by a program.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 8 of 54
R8C/3JA Group
1. Overview
1.5
Pin Functions
Tables 1.6 and 1.7 list Pin Functions. Table 1.6
Item Power supply input Analog power supply input Reset input MODE XIN clock input XIN clock output XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC
Pin Functions (1)
Pin Name VCC, VSS AVCC, AVSS RESET MODE XIN XOUT XCIN XCOUT INT0 to INT3 KI0 to KI3 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Type - - I I I I/O I O I I I/O O O I I I/O I/O Description Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins (1). To use an external clock, input it to the XOUT pin and leave the XIN pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins (1). To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. INT0 is timer RB, RC and RD input pin. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Timer RD I/O pins
Timer RD
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK TREO CLK0, CLK1, CLK2 RXD0, RXD1, RXD2 TXD0, TXD1, TXD2 CTS2 RTS2 SCL2 SDA2
I O I/O I O I O I/O I/O I/O I/O I/O I/O I/O I/O
External clock input pin Divided clock output pin Transfer clock I/O pins Serial data input pins Serial data output pins Transmission control input pin Reception control output pin I2C mode clock I/O pin I2C mode data I/O pin Clock I/O pin Data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin
Timer RE Serial interface
I2C bus SSU
SCL SDA SSI SCS SSCK SSO
I: Input O: Output I/O: Input and output Note: 1. Refer to the oscillator manufacturer for oscillation characteristics.
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R8C/3JA Group
1. Overview
Table 1.7
Item
Pin Functions (2)
Pin Name I/O Type I I I O I I O I I I I/O Description Reference voltage input pin to A/D converter and D/A converter Analog input pins to A/D converter AD external trigger input pin D/A converter output pins Comparator A analog voltage input pins Comparator A reference voltage input pin Comparator A output pins Comparator B analog voltage input pins Comparator B reference voltage input pins Detection voltage input pin for voltage detection 2 CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. All ports can be used as LED drive ports. Input-only port
Reference voltage VREF input A/D converter AN0 to AN1, AN3 to AN6, AN8 to AN11 ADTRG D/A converter Comparator A DA0, DA1 LVCMP1, LVCMP2 LVREF LVCOUT1, LVCOUT2 Comparator B Voltage detection circuit I/O port IVCMP1, IVCMP3 IVREF1, IVREF3 LVCMP2 P0_1 to P0_4, P0_6, P0_7, P1_0 to P1_7, P2_0 to P2_5, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6_6 P4_2 O: Output I/O: Input and output
Input port I: Input
I
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R8C/3JA Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers (1) Frame base register (1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
Note: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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R8C/3JA Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/3JA Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/3JA Group
3. Memory
3.
3.1
Memory
R8C/3JA Group
Figure 3.1 is a Memory Map of R8C/3JA Group. The R8C/3JA Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh 00400h
SFR (Refer to 4. Special Function Registers (SFRs))
Internal RAM
0XXXXh
0FFD8h
Reserved area
SFR (Refer to 4. Special Function Registers (SFRs))
02C00h 02FFFh 03000h
0FFDCh
Internal ROM (data flash) (1) 03FFFh 0YYYYh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer, oscillation stop detection, voltage monitor
Internal ROM (program ROM)
0FFFFh
0FFFFh
Address break (Reserved) Reset
Internal ROM (program ROM)
ZZZZZh FFFFFh
Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. The blank areas are reserved and cannot be accessed by users. Internal ROM Size 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0E000h 0C000h 0A000h 08000h Address ZZZZZh - - - - Size 1 Kbyte 1.5 Kbytes 2 Kbytes 2.5 Kbytes Internal RAM Address 0XXXXh 007FFh 009FFh 00BFFh 00DFFh
Part Number R5F213J2ANNP R5F213J4ANNP R5F213J5ANNP R5F213J6ANNP
Figure 3.1
Memory Map of R8C/3JA Group
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R8C/3JA Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.13 lists the ID Code Areas and Option Function Select Area. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h
SFR Information (1) (1)
Register Symbol After Reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register
PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC
00h 00h 00101000b 00100000b 00h 00h 00h 0XXXXXXXb (2) 00000100b XXh XXh 00111111b
Count Source Protection Mode Register
CSPR
00h 10000000b (3)
On-Chip Reference Voltage Control Register Clock Prescaler Reset Flag
OCVREFCR CPSRF
00h 00h
Voltage Monitor Circuit/Comparator A Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2
CMPA VCAC VCA1 VCA2
00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b
Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register
VD1LS VW0C
0039h Voltage Monitor 1 Circuit Control Register VW1C X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0.
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.2
SFR Information (2) (1)
Symbol VW2C After Reset 10000010b
Address Register 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control Register 004Bh UART2 Transmit Interrupt Control Register 004Ch UART2 Receive Interrupt Control Register 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register (2) 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h UART1 Transmit Interrupt Control Register 0054h UART1 Receive Interrupt Control Register 0055h INT2 Interrupt Control Register 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh 005Ch 005Dh INT0 Interrupt Control Register 005Eh UART2 Bus Collision Detection Interrupt Control Register 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1/Compare A1 Interrupt Control Register 0073h Voltage Monitor 2/Compare A2 Interrupt Control Register 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by the IICSEL bit in the SSUIICSR register.
FMRDYIC
XXXXX000b
TRCIC TRD0IC TRD1IC TREIC S2TIC S2RIC KUPIC ADIC SSUIC / IICIC S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0IC U2BCNIC
XX00X000b XXXXX000b
VCMP1IC VCMP2IC
XXXXX000b XXXXX000b
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 16 of 54
R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.3
SFR Information (3) (1)
Symbol DTCTL After Reset 00h
Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch DTC Activation Enable Register 4 008Dh DTC Activation Enable Register 5 008Eh DTC Activation Enable Register 6 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h UART0 Bit Rate Register 00A2h UART0 Transmit Buffer Register 00A3h 00A4h UART0 Transmit/Receive Control Register 0 00A5h UART0 Transmit/Receive Control Register 1 00A6h UART0 Receive Buffer Register 00A7h 00A8h UART2 Transmit/Receive Mode Register 00A9h UART2 Bit Rate Register 00AAh UART2 Transmit Buffer Register 00ABh 00ACh UART2 Transmit/Receive Control Register 0 00ADh UART2 Transmit/Receive Control Register 1 00AEh UART2 Receive Buffer Register 00AFh 00B0h UART2 Digital Filter Function Select Register 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 00BCh UART2 Special Mode Register 4 00BDh UART2 Special Mode Register 3 00BEh UART2 Special Mode Register 2 00BFh UART2 Special Mode Register X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 DTCEN5 DTCEN6
00h 00h 00h 00h 00h 00h 00h
U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h
U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR
00h 00h 000X0X0Xb X0000000b X0000000b
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.4
SFR Information (4) (1)
Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After Reset XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb
Address Register 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D Register 6 00CDh 00CEh A/D Register 7 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register 00D5h A/D Input Select Register 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h D/A0 Register 00D9h D/A1 Register 00DAh 00DBh 00DCh D/A Control Register 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h Port P2 Register 00E5h Port P3 Register 00E6h Port P2 Direction Register 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h 00EAh Port P4 Direction Register 00EBh 00ECh Port P6 Register 00EDh 00EEh Port P6 Direction Register 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
ADMOD ADINSEL ADCON0 ADCON1 DA0 DA1
00h 11000000b 00h 00h 00h 00h
DACON
00h
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6
XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h XXh 00h
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.5
SFR Information (5) (1)
Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After Reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh
Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control Register 0109h Timer RB One-Shot Control Register 010Ah Timer RB I/O Control Register 010Bh Timer RB Mode Register 010Ch Timer RB Prescaler Register 010Dh Timer RB Secondary Register 010Eh Timer RB Primary Register 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Second Data Register / Counter Data Register 0119h Timer RE Minute Data Register / Compare Data Register 011Ah Timer RE Hour Data Register 011Bh Timer RE Day of Week Data Register 011Ch Timer RE Control Register 1 011Dh Timer RE Control Register 2 011Eh Timer RE Count Source Select Register 011Fh 0120h Timer RC Mode Register 0121h Timer RC Control Register 1 0122h Timer RC Interrupt Enable Register 0123h Timer RC Status Register 0124h Timer RC I/O Control Register 0 0125h Timer RC I/O Control Register 1 0126h Timer RC Counter 0127h 0128h Timer RC General Register A 0129h 012Ah Timer RC General Register B 012Bh 012Ch Timer RC General Register C 012Dh 012Eh Timer RC General Register D 012Fh 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h Timer RC Trigger Control Register 0134h 0135h Timer RD Control Expansion Register 0136h Timer RD Trigger Control Register 0137h Timer RD Start Register 0138h Timer RD Mode Register 0139h Timer RD PWM Mode Register 013Ah Timer RD Function Control Register 013Bh Timer RD Output Master Enable Register 1 013Ch Timer RD Output Master Enable Register 2 013Dh Timer RD Output Control Register 013Eh Timer RD Digital Filter Function Select Register 0 013Fh Timer RD Digital Filter Function Select Register 1 Note: 1. The blank areas are reserved and cannot be accessed by users.
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR TRDECR TRDADCR TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1
00h 00h 00h 00h 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h 00h 00h 11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.6
SFR Information (6) (1)
Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 U1MR U1BRG U1TB U1C0 U1C1 U1RB After Reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
Address Register 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt Enable Register 0 0145h Timer RD PWM Mode Output Level Control Register 0 0146h Timer RD Counter 0 0147h 0148h Timer RD General Register A0 0149h 014Ah Timer RD General Register B0 014Bh 014Ch Timer RD General Register C0 014Dh 014Eh Timer RD General Register D0 014Fh 0150h Timer RD Control Register 1 0151h Timer RD I/O Control Register A1 0152h Timer RD I/O Control Register C1 0153h Timer RD Status Register 1 0154h Timer RD Interrupt Enable Register 1 0155h Timer RD PWM Mode Output Level Control Register 1 0156h Timer RD Counter 1 0157h 0158h Timer RD General Register A1 0159h 015Ah Timer RD General Register B1 015Bh 015Ch Timer RD General Register C1 015Dh 015Eh Timer RD General Register D1 015Fh 0160h UART1 Transmit/Receive Mode Register 0161h UART1 Bit Rate Register 0162h UART1 Transmit Buffer Register 0163h 0164h UART1 Transmit/Receive Control Register 0 0165h UART1 Transmit/Receive Control Register 1 0166h UART1 Receive Buffer Register 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 20 of 54
R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh
SFR Information (7) (1)
Register Timer RA Pin Select Register Timer RB/RC Pin Select Register Timer RC Pin Select Register 0 Timer RC Pin Select Register 1 Timer RD Pin Select Register 0 Timer RD Pin Select Register 1 Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 TRDPSR0 TRDPSR1 After Reset 00h 00h 00h 00h 00h 00h
UART0 Pin Select Register UART1 Pin Select Register UART2 Pin Select Register 0 UART2 Pin Select Register 1 SSU/IIC Pin Select Register INT Interrupt Input Pin Select Register I/O Function Pin Select Register
U0SR U1SR U2SR0 U2SR1 SSUIICSR INTSR PINSR
00h 00h 00h 00h 00h 00h 00h
SS Bit Counter Register SS Transmit Data Register L / IIC bus Transmit Data Register (2) SS Transmit Data Register H (2) SS Receive Data Register L / IIC bus Receive Data Register (2) SS Receive Data Register H (2) SS Control Register H / IIC bus Control Register 1 (2) SS Control Register L / IIC bus Control Register 2 (2) SS Mode Register / IIC bus Mode Register (2) SS Enable Register / IIC bus Interrupt Enable Register (2) SS Status Register / IIC bus Status Register (2) SS Mode Register 2 / Slave Address Register (2)
SSBR SSTDR / ICDRT SSTDRH SSRDR / ICDRR SSRDRH SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR
11111000b FFh FFh FFh FFh 00h 01111101b 00010000b / 00011000b 00h 00h / 0000X000b 00h
Flash Memory Status Register Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2
FST FMR0 FMR1 FMR2
10000X00b 00h 00h 00h
X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 21 of 54
R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.8
SFR Information (8) (1)
Symbol RMAD0 After Reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb 00h
Address Register 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register 01F1h Port P2 Drive Capacity Control Register 01F2h Drive Capacity Control Register 0 01F3h Drive Capacity Control Register 1 01F4h 01F5h Input Threshold Control Register 0 01F6h Input Threshold Control Register 1 01F7h 01F8h Comparator B Control Register 0 01F9h 01FAh External Input Enable Register 0 01FBh 01FCh INT Input Filter Select Register 0 01FDh 01FEh Key Input Enable Register 0 01FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
AIER0 RMAD1
AIER1
PUR0 PUR1
00h 00h
P1DRR P2DRR DRR0 DRR1 VLT0 VLT1 INTCMP INTEN INTF KIEN
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.9
SFR Information (9) (1)
Symbol XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset
Address Register 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer Vector Area 2C08h DTC Transfer Vector Area 2C09h DTC Transfer Vector Area 2C0Ah DTC Transfer Vector Area : DTC Transfer Vector Area : DTC Transfer Vector Area 2C3Ah DTC Transfer Vector Area 2C3Bh DTC Transfer Vector Area 2C3Ch DTC Transfer Vector Area 2C3Dh DTC Transfer Vector Area 2C3Eh DTC Transfer Vector Area 2C3Fh DTC Transfer Vector Area 2C40h DTC Control Data 0 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h DTC Control Data 1 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h DTC Control Data 2 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h DTC Control Data 3 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h DTC Control Data 4 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h DTC Control Data 5 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 23 of 54
R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.10
SFR Information (10) (1)
Symbol DTCD6 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
Address Register 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTC Control Data 9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC Control Data 13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
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R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.11
SFR Information (11) (1)
Symbol DTCD14 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
Address Register 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC Control Data 17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h DTC Control Data 18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTC Control Data 19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTC Control Data 20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTC Control Data 21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 25 of 54
R8C/3JA Group
4. Special Function Registers (SFRs)
Table 4.12
Address 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh
SFR Information (12) (1)
Register DTC Control Data 22 Symbol DTCD22 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
DTC Control Data 23
DTCD23
X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
Table 4.13
ID Code Areas and Option Function Select Area
Address Register Symbol After Reset : FFDBh Option Function Select Register 2 OFS2 (Note 1) : FFDFh ID1 (Note 2) : FFE3h ID2 (Note 2) : FFEBh ID3 (Note 2) : FFEFh ID4 (Note 2) : FFF3h ID5 (Note 2) : FFF7h ID6 (Note 2) : FFFBh ID7 (Note 2) : FFFFh Option Function Select Register OFS (Note 1) Notes: 1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select area is set to FFh. When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user. When factory-programming products are shipped, the value of the option function select area is the value programmed by the user. 2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh. When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user. When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
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R8C/3JA Group
5. Electrical Characteristics
5.
Electrical Characteristics
Table 5.1
Symbol VCC/AVCC VI VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature -40C Topr 85C
Absolute Maximum Ratings
Parameter Supply voltage Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 500 -20 to 85 (N version) -65 to 150 Unit V V V mW C C
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R8C/3JA Group
5. Electrical Characteristics
Table 5.2
Symbol
Recommended Operating Conditions
Parameter Conditions Standard Min. 1.8 - 0.8 VCC 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V Input level selection : 0.5 VCC Input level selection : 0.7 VCC 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V 0.5 VCC 0.55 VCC 0.65 VCC 0.65 VCC 0.7 VCC 0.8 VCC 0.85 VCC 0.85 VCC 0.85 VCC 0 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V Input level selection : 0.5 VCC Input level selection : 0.7 VCC 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V 4.0 V VCC 5.5 V 2.7 V VCC < 4.0 V 1.8 V VCC < 2.7 V 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - 2.7 V VCC 5.5 V 1.8 V VCC < 2.7 V 1.8 V VCC 5.5 V 2.7 V VCC 5.5 V 1.8 V VCC < 2.7 V 2.7 V VCC 5.5 V 1.8 V VCC < 2.7 V - - - - - - - CMOS Input level input switching function (I/O port) Input level selection : 0.35 VCC Typ. - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32.768 - - - - Max. 5.5 - VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.55 VCC 0.45 VCC 0.35 VCC -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 5 50 20 5 20 5 Unit V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz kHz MHz MHz MHz MHz
VCC/AVCC Supply voltage VSS/AVSS Supply voltage VIH Input "H" voltage Other than CMOS input
VIL
Input "L" voltage Other than CMOS input CMOS Input level input switching function (I/O port) Input level selection : 0.35 VCC
IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN) f(XCIN) - f(BCLK)
Peak sum output Sum of all pins IOH(peak) "H" current Average sum Sum of all pins IOH(avg) output "H" current Peak output "H" current Average output "H" current Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High
Peak sum output Sum of all pins IOL(peak) "L" current Average sum Sum of all pins IOL(avg) output "L" current Peak output "L" current Average output "L" current Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High
XIN clock input oscillation frequency XCIN clock input oscillation frequency System clock frequency CPU clock frequency
Notes: 1. VCC = 1.8 to 5.5 V at Topr = -20 to 85C (N version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms.
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5. Electrical Characteristics
P0 P1 P2 P3 P4 P6
30 pF
Figure 5.1
Ports P0 to P4, P6 Timing Measurement Circuit
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5. Electrical Characteristics
Table 5.3
Symbol - -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode Vref = AVCC Vref = AVCC = 5.0 V AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input AN0 to AN1 input, AN3 to AN6 input, AN8 to AN11 input Conditions Standard Min. - - Typ. - - Max. 10 3 Unit Bit LSB
Vref = AVCC = 3.3 V
-
-
5
LSB
Vref = AVCC = 3.0 V
-
-
5
LSB
Vref = AVCC = 2.2 V
-
-
5
LSB
8-bit mode
Vref = AVCC = 5.0 V
-
-
2
LSB
Vref = AVCC = 3.3 V
-
-
2
LSB
Vref = AVCC = 3.0 V
-
-
2
LSB
Vref = AVCC = 2.2 V
-
-
2
LSB
AD
A/D conversion clock
4.0 V Vref = AVCC 5.5 V (2) 3.2 V Vref = AVCC 5.5 V (2) 2.7 V Vref = AVCC 5.5 V (2) 2.2 V Vref = AVCC 5.5 V
(2)
2 2 2 2 - -
- - - - 3 - - - - 45 - -
20 16 10 5 - 1 - - - - AVCC Vref
MHz MHz MHz MHz k LSB s s s A V V
- DNL tCONV tSAMP IVref Vref VIA
Tolerance level impedance Differential non-linearity error Conversion time Sampling time Vref current Reference voltage Analog input voltage (3) 10-bit mode 8-bit mode Vref = AVCC = 5.0 V, AD = 20 MHz Vref = AVCC = 5.0 V, AD = 20 MHz AD = 20 MHz VCC = 5 V, XIN = f1 = AD = 20 MHz
2.15 2.15 0.75 - 2.2 0
Notes: 1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version), unless otherwise specified. 2. When the CPU and flash memory stop, the A/D conversion result will be undefined. 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
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5. Electrical Characteristics
Table 5.4
Symbol - - tsu RO IVref
D/A Converter Characteristics
Parameter Resolution Absolute accuracy Setup time Output resistor Reference power input current (Note 2) Conditions Standard Min. - - - - - Typ. - - - 6 - Max. 8 2.5 3 - 1.5 Unit Bit LSB s k mA
Notes: 1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = -20 to 85C (N version), unless otherwise specified. 2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h. The resistor ladder of the A/D converter is not included.
Table 5.5
Symbol LVREF LVCMP1, LVCMP2 - -
Comparator A Electrical Characteristics
Parameter External reference voltage input range External comparison voltage input range Offset Comparator output delay time
(2)
Condition
Standard Min. 1.4 -0.3 - Typ. - - 50 3 1.5 2 0.5 0.5 Max. VCC VCC + 0.3 200 - - - - -
Unit V V mV s s s s A
At falling, VI = Vref - 100 mV At falling, VI = Vref - 1 V or below At rising, VI = Vref + 100 mV At rising, VI = Vref + 1 V or above
- - - - -
-
Comparator operating current
VCC = 5.0 V
Notes: 1. VCC = 2.7 to 5.5 V, Topr = -20 to 85C (N version), unless otherwise specified. 2. When the digital filter is disabled.
Table 5.6
Symbol Vref VI - td ICMP
Comparator B Electrical Characteristics
Parameter IVREF1, IVREF3 input reference voltage IVCMP1, IVCMP3 input voltage Offset Comparator output delay time (2) Comparator operating current VI = Vref 100 mV VCC = 5.0 V Condition Standard Min. 0 -0.3 - - - Typ. - - 5 0.1 17.5 Max. VCC - 1.4 VCC + 0.3 100 - - Unit V V mV s A
Notes: 1. VCC = 2.7 to 5.5 V, Topr = -20 to 85C (N version), unless otherwise specified. 2. When the digital filter is disabled.
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5. Electrical Characteristics
Table 5.7
Symbol - - - td(SR-SUS) - - - - - - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance (2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for autoerasure to complete Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55C Conditions Standard Min. 1,000 (3) - - - 33 33 - 2.7 1.8 0 20 Typ. - 80 0.3 - - - - - - - - Max. - - - 5+CPU clock x 3 cycles - - 30+CPU clock x 1 cycle 5.5 5.5 60 - Unit times s s ms ms ms s V V C year
Notes: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
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5. Electrical Characteristics
Table 5.8
Symbol - - - - - td(SR-SUS) - - - - - - -
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Parameter Program/erase endurance (2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for autoerasure to complete Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55C Conditions Standard Min. 10,000 (3) - - - - - 33 33 - 2.7 1.8 -20 20 Typ. - 160 300 0.2 0.3 - - - - - - - - Max. - - - - - 5+CPU clock x 3 cycles - - 30+CPU clock x 1 cycle 5.5 5.5 85 - Unit times s s s s ms ms ms s V V C year
Notes: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request (FMR21 bit)
FST6 bit
Fixed time Clock-dependent time Access restart
td(SR-SUS)
FST6: Bit in FST register FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
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5. Electrical Characteristics
Table 5.9
Symbol Vdet0
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet0_0 (2) Voltage detection level Vdet0_1 (2) Voltage detection level Vdet0_2 Voltage detection level Vdet0_3
(2) (2)
Condition
Standard Min. 1.80 2.15 2.65 3.55 Typ. 1.90 2.35 2.85 3.80 6 1.5 - Max. 2.05 2.50 3.00 4.05 150 - 100
Unit V V V V s A s
- - td(E-A)
Voltage detection 0 circuit response time (4) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3)
At the falling of VCC from 5 V to (Vdet0_0 - 0.1) V VCA25 = 1, VCC = 5.0 V
- - -
Notes: 1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = -20 to 85C (N version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. 4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.10
Symbol Vdet1
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet1_0 (2) Voltage detection level Vdet1_1
(2)
Condition At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC Vdet1_0 to Vdet1_5 selected Vdet1_6 to Vdet1_F selected
Standard Min. 2.00 2.15 2.30 2.45 2.60 2.75 2.90 3.05 3.20 3.35 3.50 3.65 3.80 3.95 4.10 4.25 - - - - - Typ. 2.20 2.35 2.50 2.65 2.80 2.95 3.10 3.25 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 0.07 0.10 60 1.7 - Max. 2.40 2.55 2.70 2.85 3.00 3.15 3.30 3.45 3.60 3.75 3.90 4.05 4.20 4.35 4.50 4.65 - - 150 - 100
Unit V V V V V V V V V V V V V V V V V V s A s
Voltage detection level Vdet1_2 (2) Voltage detection level Vdet1_3 (2) Voltage detection level Vdet1_4 (2) Voltage detection level Vdet1_5 Voltage detection level Vdet1_6
(2) (2)
Voltage detection level Vdet1_7 (2) Voltage detection level Vdet1_8 (2) Voltage detection level Vdet1_9 Voltage detection level Vdet1_A
(2) (2)
Voltage detection level Vdet1_B (2) Voltage detection level Vdet1_C (2) Voltage detection level Vdet1_D Voltage detection level Vdet1_E -
(2) (2)
Voltage detection level Vdet1_F (2) Hysteresis width at the rising of Vcc in voltage detection 1 circuit
- - td(E-A) Notes: 1. 2. 3. 4.
Voltage detection 1 circuit response time (3) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (4)
At the falling of VCC from 5 V to (Vdet1_0 - 0.1) V VCA26 = 1, VCC = 5.0 V
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = -20 to 85C (N version). Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
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5. Electrical Characteristics
Table 5.11
Symbol Vdet2 - - - td(E-A) Notes: 1. 2. 3. 4.
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet2_0 (2) Voltage detection level Vdet2_EXT (2) Hysteresis width at the rising of Vcc in voltage detection 2 circuit Voltage detection 2 circuit response time (3) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (4) At the falling of VCC from 5 V to (Vdet2_0 - 0.1) V VCA27 = 1, VCC = 5.0 V Condition At the falling of VCC At the falling of LVCMP2 Standard Min. 3.70 1.20 - - - - Typ. 4.00 1.34 0.10 20 1.7 - Max. 4.30 1.48 - 150 - 100 Unit V V V s A s
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = -20 to 85C (N version). The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
Table 5.12
Symbol trth
Power-on Reset Circuit (2)
Parameter External power VCC rise gradient Condition Standard Min. 0 Typ. - Max. 50000 Unit mV/msec
Notes: 1. The measurement condition is Topr = -20 to 85C (N version), unless otherwise specified. 2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1) trth External Power VCC 0.5 V tw(por) (2) Voltage detection 0 circuit response time trth
Vdet0 (1)
Internal reset signal
1 x 32 fOCO-S
1 x 32 fOCO-S
Notes: V . o e g a t l D i c C n u r 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6of Hardware Manual (REJ09B0508) for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
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5. Electrical Characteristics
Table 5.13
Symbol fOCO-S - -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25C VCC = 5.0 V, Topr = 25C Condition Standard Min. 60 - - Typ. 125 30 2 Max. 250 100 - Unit kHz s A
Note: 1. VCC = 1.8 to 5.5 V, Topr = -20 to 85C (N version), unless otherwise specified.
Table 5.14
Symbol td(P-R)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on (2) Condition Standard Min. - Typ. - Max. 2000 Unit s
Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
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5. Electrical Characteristics
Table 5.15
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Synchronous Serial Communication Unit (SSU) (1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time Master Slave Master Slave Conditions Standard Min. 4 0.4 0.4 - - - - 100 1 1tCYC + 50 1tCYC + 50 - 2.7 V VCC 5.5 V 1.8 V VCC < 2.7 V SSI slave out open time 2.7 V VCC 5.5 V 1.8 V VCC < 2.7 V - - - - Typ. - - - - - - - - - - - - - - - - Max. - 0.6 0.6 1 1 1 1 - - - - 1 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200 Unit tCYC (2) tSUCYC tSUCYC tCYC (2) s tCYC (2) s ns tCYC (2) ns ns tCYC (2) ns ns ns ns
SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time SCS hold time SSI slave access time Slave Slave
SSO, SSI data output delay time
Notes: 1. VCC = 1.8 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
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5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
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5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIL or VOL tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
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5. Electrical Characteristics
tHI VIH or VOH
SSCK
VIL or VOL tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.6
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous Communication Mode)
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5. Electrical Characteristics
Table 5.16
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH
Timing Requirements of I2C bus Interface (1)
Parameter SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Condition Standard Typ. (2) - 12tCYC + 600 Min. 3tCYC + 300
(2)
Max. -
- -
Unit ns ns ns ns ns ns ns ns ns ns ns
- - - - - - - - - -
5tCYC + 500 (2) - - 5tCYC 3tCYC
(2) (2)
300 1tCYC (2) -
- - - - -
3tCYC (2) 3tCYC (2) 1tCYC + 40 (2) 10
Notes: 1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = -20 to 85C (N version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP
SCL
P(2) S(1) tsf tSCLL tSCL Sr(3) tsr tSDAH tSDAS P(2)
Notes: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
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5. Electrical Characteristics
Table 5.17
Symbol VOH VOL VT+-VT-
Electrical Characteristics (1) [4.2 V Vcc 5.5 V]
Parameter Condition Drive capacity High VCC = 5.0V Drive capacity Low VCC = 5.0V Drive capacity High VCC = 5.0V Drive capacity Low VCC = 5.0V IOH = -20 mA IOH = -5 mA IOL = 20 mA IOL = 5 mA Standard Min. Typ. VCC - 2.0 - VCC - 2.0 - - - - - 0.1 1.2 Max. VCC VCC 2.0 2.0 - Unit V V V V V
Output "H" voltage Output "L" voltage Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRDIOA0, TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSO
RESET Input "H" current IIH IIL Input "L" current RPULLUP Pull-up resistance RfXIN Feedback XIN resistance RfXCIN Feedback XCIN resistance VRAM RAM hold voltage
0.1 VI = 5 V, VCC = 5.0 V VI = 0 V, VCC = 5.0 V VI = 0 V, VCC = 5.0 V
- -
1.2
- -
-
V
A A k M
5.0
-5.0
25 -
-
50 0.3 8
-
100 -
- -
M V
During stop mode
1.8
Note: 1. 4.2 V VCC 5.5 V at Topr = -20 to 85C (N version), f(XIN) = 20 MHz, unless otherwise specified.
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5. Electrical Characteristics
Table 5.18
Electrical Characteristics (2) [3.3 V Vcc 5.5 V] (Topr = -20 to 85C (N version), unless otherwise specified.)
Parameter Condition Min. - Standard Typ. Max. 6.5 15 Unit mA
Symbol ICC
Power supply current High-speed XIN = 20 MHz (square wave) (VCC = 3.3 to 5.5 V) clock mode Low-speed on-chip oscillator on = 125 kHz No division Single-chip mode, output pins are open, XIN = 16 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz other pins are VSS
No division XIN = 10 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz Divide-by-8
-
5.3
12.5
mA
-
3.6
-
mA
-
3.0
-
mA
-
2.2
-
mA
-
1.5
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0
-
90
400
A
-
85
400
A
-
47
-
A
Wait mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
-
15
100
A
-
4
90
A
-
3.5
-
A
Stop mode
XIN clock off, Topr = 25C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
-
2.0
5.0
A
-
5.0
-
A
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 43 of 54
R8C/3JA Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) Table 5.19
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 50 - 24 - 24 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN)
Figure 5.8 Table 5.20
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
XIN Input and XCIN Input Timing Diagram when VCC = 5 V TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 44 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.21
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 to 2
Figure 5.10
Serial Interface Timing Diagram when VCC = 5 V
Table 5.22
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. Max. - 250 (1) 250 (2)
-
Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
tW(INL)
tW(INH)
Figure 5.11
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 45 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.23
Symbol VOH VOL VT+-VT-
Electrical Characteristics (3) [2.7 V Vcc < 4.2 V]
Parameter Condition Drive capacity High Drive capacity Low Drive capacity High Drive capacity Low VCC = 3.0 V IOH = -5 mA IOH = -1 mA IOL = 5 mA IOL = 1 mA Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - - - - - 0.1 0.4 Max. VCC VCC 0.5 0.5 - Unit V V V V V
Output "H" voltage Output "L" voltage Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRDIOA0, TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSO RESET
VCC = 3.0 V VI = 3 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V
0.1
- -
0.5
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Feedback resistance XCIN RAM hold voltage
4.0
-4.0
During stop mode
42 - - 1.8
84 0.3 8 -
168 - - -
Note: 1. 2.7 V VCC < 4.2 V at Topr = -20 to 85C (N version), f(XIN) = 10 MHz, unless otherwise specified.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 46 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.24
Electrical Characteristics (4) [2.7 V Vcc < 3.3 V] (Topr = -20 to 85C (N version), unless otherwise specified.)
Parameter Condition Min. - Standard Typ. Max. 3.5 10 Unit mA
Symbol ICC
Power supply current High-speed XIN = 10 MHz (square wave) (VCC = 2.7 to 3.3 V) clock mode Low-speed on-chip oscillator on = 125 kHz No division Single-chip mode, output pins are open, XIN = 10 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz other pins are VSS
Divide-by-8
-
1.5
7.5
mA
Low-speed on-chip oscillator mode Low-speed clock mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0
-
90
390
A
-
80
400
A
-
40
-
A
Wait mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
-
15
90
A
-
4
80
A
-
3.5
-
A
Stop mode
XIN clock off, Topr = 25C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
-
2.0
5.0
A
-
5.0
-
A
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 47 of 54
R8C/3JA Group
Timing Requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) Table 5.25
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 50 - 24 - 24 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN)
Figure 5.12 Table 5.26
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
XIN Input and XCIN Input Timing Diagram when VCC = 3 V TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 48 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.27
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 to 2
Figure 5.14
Serial Interface Timing Diagram when VCC = 3 V
Table 5.28
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. Max. - 380 (1) 380 (2)
-
Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
VCC = 3 V
tW(INL)
tW(INH)
Figure 5.15
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 49 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.29
Symbol VOH VOL VT+-VT-
Electrical Characteristics (5) [1.8 V Vcc < 2.7 V]
Parameter Standard Min. Typ. Drive capacity High IOH = -2 mA VCC - 0.5 - Drive capacity Low IOH = -1 mA VCC - 0.5 - Drive capacity High IOL = 2 mA - - Drive capacity Low IOL = 1 mA - - 0.05 0.2 Condition Max. VCC VCC 0.5 0.5 - Unit V V V V V
Output "H" voltage Output "L" voltage Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRDIOA0, TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRCTRG, TRCCLK, ADTRG, RXD0, RXD1, RXD2, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSO RESET
0.05 VI = 2.2 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V
- -
0.20
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Feedback resistance XCIN RAM hold voltage
4.0
-4.0
During stop mode
70 - - 1.8
140 0.3 8 -
300 - - -
Note: 1. 1.8 V VCC < 2.7 V at Topr = -20 to 85C (N version), f(XIN) = 5 MHz, unless otherwise specified.
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 50 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.30
Electrical Characteristics (6) [1.8 V Vcc < 2.7 V] (Topr = -20 to 85C (N version), unless otherwise specified.)
Parameter Condition Min. - Standard Typ. Max. 2.2 - Unit mA
Symbol ICC
Power supply current High-speed XIN = 5 MHz (square wave) (VCC = 1.8 to 2.7 V) clock mode Low-speed on-chip oscillator on = 125 kHz No division Single-chip mode, output pins are open, XIN = 5 MHz (square wave) Low-speed on-chip oscillator on = 125 kHz other pins are VSS
Divide-by-8
-
0.8
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0
-
90
300
A
-
80
350
A
-
40
-
A
Wait mode
XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
-
15
90
A
-
4
80
A
-
3.5
-
A
Stop mode
XIN clock off, Topr = 25C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
-
2.0
5
A
-
5.0
-
A
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 51 of 54
R8C/3JA Group
Timing Requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) Table 5.31
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 200 - 90 - 90 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 2.2 V
XIN input
tWL(XIN)
Figure 5.16 Table 5.32
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 500 - 200 - 200 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 52 of 54
R8C/3JA Group
5. Electrical Characteristics
Table 5.33
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 800 - 400 - 400 - - 200 0 - 150 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 to 2
Figure 5.18
Serial Interface Timing Diagram when VCC = 2.2 V
Table 5.34
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. Max. - 1000 (1) 1000 (2)
-
Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
VCC = 2.2 V
tW(INL)
tW(INH)
Figure 5.19
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 2.2 V
REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 53 of 54
R8C/3JA Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-HWQFN36-6x6-0.50 RENESAS Code PWQN0036KA-B Previous Code 36PJW-B MASS[Typ.] 0.07g
*1 D
27
19
19
27
28
18
18
28
D2
*2
E
Lp 36 10 10 36
E1
1
9
9 e bp x
1
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH.
Reference Dimension in Millimeters Symbol
F
y Detail F
D E A2 A A1 bp e Lp x y D2 E1
Nom Max 6.0 6.1 6.0 6.1 0.75 0.8 0 0 0.05 0.15 0.2 0.25 0.5 0.5 0.6 0.7 0.05 0.05 2.9 2.9
Min 5.9 5.9
A2
REJ03B0263-0110 Rev.1.10 Page 54 of 54
Sep 30, 2009
A1
A
REVISION HISTORY REVISION HISTORY
Rev. 0.10 0.20 Date Jul 15, 2008 Oct 10, 2008
R8C/3JA Group Datasheet R8C/3JA Group Datasheet
Description
Page
-
Summary First Edition issued 1.1 "These MCUs also use an anti-noise .... to withstand EMI." "These MCUs are designed to maximize EMI/EMS performance." Table 1.1 revised Table 1.2 revised Figure 1.2 revised Table 1.5 Pin Number 31: "(TRCIOB/TREO)" "TREO/(TRCIOB)" Table 4.1 Note 2 revised Table 4.2 0046h deleted Table 4.4 00C0h "XXXh" "XXh" Table 4.8 01FBh, 01FDh deleted
1 2 3 5 8 15 16 18 22
27 to 53 5. Electrical Characteristics added 1.00 Sep 10, 2009 All pages "Preliminary" "Under development" "High-speed on-chip oscillator" deleted 4 6, 7 9 14 21 26 28 30 32, 33 34 35 36 Table 1.3 revised, Figure 1.1 deleted Figure 1.3, Table 1.4 "(/XCOUT)" "(/XCIN)" deleted Table 1.5 Note 2 deleted Figure 3.1 "R5F213J1ANNP, R5F213J1ADNP" deleted Table 4.7 0186h deleted, 019Ah "00010000b/" added Table 4.12 revised, Table 4.13 added Table 5.2 revised, Note 3 deleted Table 5.3 "2.2 V Vref = AVCC 5.5 V" "2.2 V Vref = AVCC 5.5 V (2)" Table 5.7, Table 5.8 revised Table 5.9, Table 5.10 revised Table 5.11, Table 5.12, Figure 5.3 revised Old Table 5.13 deleted
38 to 40 Figure 5.4 to Figure 5.6 "VIH or VOH" "VIL or VOL" 42, 46, 50 Table 5.17, Table 5.23, Table 5.29 revised 43, 47, 51 Table 5.18, Table 5.24, Table 5.30 revised 45, 49, 53 Table 5.22, Table 5.28, Table 5.34 INT0 INTi 1.10 Sep 30, 2009 All pages "D version" deleted, Package code revised 54 Package Dimensions revised
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